By Frank Hannig, João M.P. Cardoso, Thilo Pionteck, Dietmar Fey, Wolfgang Schröder-Preikschat, Jürgen Teich
This booklet constitutes the lawsuits of the twenty ninth overseas convention on structure of Computing structures, ARCS 2016, held in Nuremberg, Germany, in April 2016.
The 29 complete papers awarded during this quantity have been rigorously reviewed and chosen from 87 submissions. They have been geared up in topical sections named: configurable and in-memory accelerators; network-on-chip and safe computing architectures; cache architectures and protocols; mapping of purposes on heterogeneous architectures and real-time projects on multiprocessors; all approximately time: timing, tracing, and function modeling; approximate and energy-efficient computing; allocation: from thoughts to FPGA modules; natural computing platforms; and reliability elements in NoCs, caches, and GPUs.
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Additional resources for Architecture of Computing Systems -- ARCS 2016: 29th International Conference, Nuremberg, Germany, April 4-7, 2016, Proceedings
1 Design of PIM and Its Software Stack We have chosen an ARM Cortex-A15 core without caches or prefetchers for PIM, and augmented it with low cost components to enhance its capabilities. Our choice of ARM is because it oﬀers a mature software stack, its system bridges (AXI) are well understood, and it is an energy-eﬃcient architecture. Nevertheless, the architecture is not limited to it. As shown in Fig. 1a, PIM is attached to the main LoB interconnect through its own local interconnect, and features a Scratchpad Memory (SPM), a DMA engine, a Translation Look-aside Buﬀer (TLB) along with a Memory Management Unit (MMU).
As tasks (may) execute concurrently, Fig. 4- and 6-FUs) which is contrary to conventional processors which possess two ALUs. This fact is attributed to the physical compiler’s ability to extract additional ILP and DLP. Thus when only one task is to be executed at a given time, preference to is given to the larger engine which can provide the processor with higher performance and more flexibility for executing the task. Overall, the most fair utilization found among the different engine conﬁgurations tested was the <4x6> CCU which delivered almost equal utilization of its engines.
We use two DMA resources to eﬃciently hide the latency of traversing the LIL. First we study oﬄoading overheads. ATF has been executed on the host side and then oﬄoaded to PIM. In Fig. 2a, kernel-oﬄoad represents the overhead associated with reading the ELF ﬁle from the secondary storage of the host, parsing it, and oﬄoading the binary code (as explained in Subsect. 1); taskoﬄoad is all overheads associated with virtual pointer passing to PIM for the graph to be analyzed; and host-execution is the absolute execution time of the kernel on host.